Wednesday, September 08, 2010

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Building better memory management for high performance wired/wireless networks: Part 2

Evaluating the performance of variable versus fixed-size memory pools

Khaled Elsayed and Mohamed Galal

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To evaluate the performance of the proposed variable-size memory pool scheme described in Part 1 in this series - particularly as it compares with fixed-sized pools - we used discrete-event simulation to generate random requests to the memory pool.

The requests are generated in accordance with a Poisson process with a given rate. The request size is also randomly chosen from a specified range of values. The requested buffer is held for a random period of time and then released.

The simulation is run till 1 million requests are generated in each scenario. We execute multiple experiments to assess the performance of the schemes in different scenarios comprised of different loading and different request patterns and pool configurations in terms of number of partitions and partition size for the variable size pools and the number of buffer and maximum size for the fixed-size pools. The following metrics are used to capture the performance effects:

Bandwidth Admission Probability: This quantity is obtained as the ratio between the sum of the sizes of admitted allocation requests and the sum of the sizes of all allocation requests. This directly affects the overall system throughput, where the throughput is the total requested rates times the bandwidth admission probability.

Memory Utilization: This quantity reflects the extent to which the overall pool memory is utilized. This takes into account all the memory used by the pool including the overheads associated with the supporting structures and meta-data.

This is obtained by taking the overall summation of the request size times the holding time of the allocated PG/buffer and dividing it by the total system time multiplied by the overall memory size associated with the pool structure. Another related quantity is the pool memory utilization which takes into account only the memory available for use by the pool user excluding overheads.

Testing variable- vs fixed-size memory pools
In the first scenario we examine the performance of fixed and variable-size pools. We generate allocation requests with a Poisson process such that the average inter-arrival time is changed from 0.0005 to 0.0035 time units in increments of 0.005 time units.

The memory resource is reserved for an average of 1 time unit. The allocation request size varies uniformly between a minimum of 80 bytes and a maximum of 2000 bytes. The fixed size pool has a size of 2048 byte per buffer with a total number of 272 buffers whereas the variable-size pool consists of 1024 partitions each with size 512 bytes.

These configurations result in a total of 557056 bytes and 524288 bytes of user allocatable space on the fixed and variable-size pools respectively. The sizes are carefully chosen such that the overall pool memory size including overheads is almost equal in the two cases. The 3 performance metrics comparing the two schemes are provided in Figure 5 below.


Figure 5: Performance of the variable (a) on top versus fixed-size (b) memory pools below it.

As can be seen from the figure, the variable size pool performance is consistently better than the fixed-size pool in terms of bandwidth admission, overall and pool memory utilization, and also the combined utility is higher.

Moreover, it offers better acceleration in satisfying the requests as indicated by the larger slope of the line in Figure 5a. In other words, it is capable of reaching a 100% request satisfaction earlier than the fixed-pool (when the inter-arrival time is 0.003 units, the variable-size pool admits 100% requests whereas the fixed-size is still at 80%).

Figure 5b (b) indicates an interesting behavior which is there is a certain point at which the memory utilization and overall system utility is maximized after which the system is over-engineered and memory is idle. The designer needs to select the optimum size in light of the expected load and the required throughput which is governed by the bandwidth admission.

Page 2: Building better memory management for high performance wired/wireless networks: Part 2
Page 3: Building better memory management for high performance wired/wireless networks: Part 2

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